1. Field of the Invention
The invention relates to a new way of making electrically isolated pillars in silicon active devices. It has particular application to three-dimensional (3D) memories, and in particular to 3D memories that include diodes or incipient diodes (i.e., two halves of a diode separated by an antifuse layer).
2. Discussion of the Related Art
3D memories can be much lower cost than conventional 2D memories. If a conventional memory occupies X square millimeters of silicon area, then a 3D memory comprising N planes of bits occupies approximately (X/N) square millimeters of silicon area. Reduced area means that more finished memory devices can be built on a single wafer, thereby reducing cost. Thus, there is a strong incentive to pursue 3D memories having multiple planes of memory cells.
U.S. Pat. No. 6,034,882, assigned to Matrix Semiconductor, Inc. and incorporated by reference herein, describes a 3D field-programmable, non-volatile memory that is well suited to extremely small memory cells. Each memory cell includes a pillar of layers formed at the intersection between upper and lower conductors. In one embodiment, the pillar includes a steering element, such as a diode, that is connected in series with a state change element, such as an antifuse layer. In the preferred embodiment described therein, each pillar is isolated from neighboring pillars by a pair of self-aligned etch steps and interleaved dielectric depositions. When the antifuse layer is intact (i.e., the cell is not programmed), the cell is electrically an open circuit. When the antifuse layer is breached (i.e., the cell is programmed), the cell is electrically a diode in series with the resistance of the breached antifuse layer.
U.S. patent application Ser. No. 09/560,626 filed Apr. 28, 2000 and its continuation-in-part application 09/814,727 filed Mar. 21, 2001, both entitled, “Three-Dimensional Memory Array and Method of Fabrication, assigned to Matrix Semiconductor, Inc. and incorporated by reference herein, disclose, rather than pillars, a memory cell at intersections of rail stacks. The memory cell includes a combined steering element and state change element. Specifically, the disclosed memory cell includes an antifuse layer disposed between the anode and the cathode of an incipient diode. When the antifuse layer is intact, the cell is electrically an open circuit. But when the antifuse is breached, a portion of the anode material and a portion of the cathode material are fused in a small-diameter filament, thereby forming the diode.
U.S. patent application Ser. No. 09/928,536, filed Aug. 13, 2001, entitled “Vertically-Stacked, Field Programmable, Nonvolatile Memory and Method of Fabrication,” assigned to Matrix Semiconductor, Inc. and incorporated by reference herein, describes 3D memories having various pillar configurations and including antifuse and diode components.
U.S. patent application Ser. No. 09/639,577 filed Aug. 14, 2000, entitled, “Multigate Semiconductor Device with Vertical Channel Current and Method of Fabrication” assigned to Matrix Semiconductor, Inc. and incorporated by reference herein, describes 2D memories having various pillar configurations and including transistor components.
U.S. patent application Ser. No. 09/927,648 filed Aug. 13, 2001, entitled, “Dense Arrays and Charge Storage Devices, and Methods for Making Same,” assigned to Matrix Semiconductor, Inc. and incorporated by reference herein, describes 3D memories having various pillar configurations and including diode or transistor components.
When pillar structures are formed, a typical procedure would be to etch a first plurality of layers into strips in a first direction, fill the spaces in between the strips with a dielectric, deposit a second plurality of layers, and then etch both second and first plurality of layers in a second direction, orthogonal to the first. The second etch is selective to material constituting the first and second plurality of layers, and does not appreciably etch the dielectric. Accordingly, as explained in more detail below, any material within the first plurality of layers, trapped under the dielectric that is laid down after the first etch, will not be removed in the second etch. This remaining material, sometimes called a “stringer,” can provide an unintended electrical path between adjacent pillars.
Where two adjacent pillars have stringers that interfere with their electrical isolation from each other, the functioning of these memory cells can be compromised. Specifically, a write operation to one memory cell can undesirably affect one or both memory cells, i.e., a write disturb condition can occur.
Previously, stringer formation could be prevented in at least two ways: (i) by using an “aggressive,” perfectly vertical anisotropic etch, such as pure Cl2 in the case of a silicon-containing first plurality of layers, so that no dielectric (e.g., SiO2) hardmask overhang forms over a sloped sidewall of the first plurality of layers, and therefore no material from the first plurality of layers is trapped under the dielectric to form a stringer in the first place, or (ii) by using a “less aggressive etch,” i.e., an etch that results in a positive slope that causes stringers (due to the overhanging SiO2 hardmask), but following that etch by an isoptropic etch that clears away the stringer (dilute SF6 in a noble gas such as Ar, for example) after the stringers are formed. The distinction between these two approaches is that the former prevents stringers from forming, but the latter “cleans” them up after they've formed.
Nevertheless, both approaches have drawbacks. The use of etchants, such as Cl2, that typically produce quite vertical sidewalls is problematic because such etchants are so “aggressive” that they isotropically (i.e., multi-directionally) etch the refractory metal silicide conductors that are used in the devices (such as TiSi2), even though they very anisotropically (uni-directionally, e.g., vertically) etch Si. This aggressive etching is undesirable as it can cause such conductors to function unreliably. On the other hand, using a “stringer-clearing” second etch is problematic because it is very difficult to control and can etch the pillar as well as the stringer.
Therefore, a need arises for a method of accurately forming active devices, such as diodes, that is compatible with less aggressive etch chemistries.